The progress in miniaturization and multi-layering of semiconductor devices has increased current density, which has resulted in serious electromigration (EM). Multilayer wiring techniques using copper (Cu), which has a high EM resistance, is thus essential for higher integration of semiconductor devices.
A process for manufacturing Cu wires uses a so-called Damascene process, which preforms trenches in an insulation layer in correspondence with a wiring pattern and then forms wires by filling the trenches with Cu. The process for manufacturing Cu wires also uses a so-called Dual-Damascene process, which preforms via holes in wiring trenches and then simultaneously forms wires and via contacts by filling Cu into both of the trenches and the via holes.
On the Cu wires subsequent to the Damascene process, a cap layer SiC, SiN, or the like is arranged between the Cu wires and the insulation layer (e.g., low permittivity film: Low-k film), which is arranged on the Cu wires. The cap layer functions as an oxidation resistant film on surfaces of the Cu wires, a diffusion resistant film for Cu, and an etching stop film for the via holes. The adhesion of the cap layer including the insulation film of SiC, SiN, or the like with the Cu wires is weak. This lowers the reliability of the Cu wires. Furthermore, the cap layer causes the etching of the via holes to become complicated and thereby lowers the productivity of the semiconductor device.
To solve this problem, in the prior art, a Cu multilayer wiring technique using a metal material for the cap layer on Cu wires has been proposed. The cap layer formed from a metal material (hereinafter simply referred to as a metal cap layer) must have a high adhesiveness with respect to the Cu wires, a low specific resistance, and high barrier properties (high barrier properties with respect to moisture from the Low-k film and Cu atoms from the Cu wires), and selectivity so that the cap layer is formed on only the Cu wires.
Patent document 1 uses an electroless plating process to selectively deposit cobalt-tungsten phosphide (CoWP) on a Cu wire surface and form a metal cap layer on the surface of the CoWP layer through a salicide process. This satisfies the adhesiveness, conductivity, barrier properties, and film-formation selectivity required for the metal cap layer and improves the oxidation resistance of the metal cap layer.
Patent document 2 forms a metal cap layer on the entire surface of a substrate including Cu wires by using zirconium nitride, zirconium nitride compounds, or the like for the material of the metal cap layer. Zirconium nitride and zirconium nitride compound selectively provide conductivity only on the Cu wiring. This produces the functions of a metal cap layer without the need for film-formation selectivity.
However, patent document 1 uses an electroless plating process to obtain the film-formation selectivity. In the electroless plating process, the shape and film thickness of the CoWP layer are greatly affected by the concentration of chemicals, the oxidation-reduction atmosphere, and the like. As a result, the deposition state of CoWP greatly fluctuates in accordance with the coarseness/denseness, surface area, shape, etc. of the Cu wires. This leads to short-circuiting between adjacent CoWP layers and covering failures of the Cu wires.
Further, in the electroless plating process, the surface that is immersed in chemicals, such as the surface of the Cu wires subsequent to the Damascenes process and the surface of the Low-k film, must be extremely clean to realize film-formation selectivity. This increases the number of surface treatment steps involved in cleaning and thereby lowers the productivity of the semiconductor device.
Patent document 2 only discloses a manufacturing method related to zirconium nitride (ZrN) using tetrakis-diethylamino-zirconium (TDEAZ) and does not disclose the raw materials, conditions, and the like for a manufacturing method related to zirconium nitride compound. Moreover, the inventors of the present application has conducted experiments and have found that in a ZrN film formation process using TDEAZ, a large amount of powder-like ZrN and by-products are simultaneously generated and a sufficient particle level is difficult to obtain when manufacturing semiconductor devices. The powder-like ZrN and by-products accumulate in a supply system and discharge system for raw material gas and thereby interfere with stable operation of the manufacturing apparatus. Therefore, there is a demand for a manufacturing apparatus and manufacturing method for semiconductor devices that improve the reliability and productivity of the metal cap layer.
Furthermore, the demand has recently been increasing for microfabrication is accelerating in for thin film manufacturing techniques in the semiconductor field. This has raised various problems.
For example, copper is often used as wiring material due to reasons such as the resistivity being small and electromigration being less likely to occur. However, copper is difficult to etch and has a property of easily diffusing in an underlayer (silicon dioxide film). This lowers the reliability of the device.
In order to solve such problem, a barrier film is formed through CVD process or the like on an inner wall surface of an inter-multilayer connection hole in a multilayer wiring structure, and a copper thin film is formed thereon as a wiring layer. As a result, the copper thin film and the underlayer (silicon dioxide film) do not come into direct contact. This prevents the diffusion of copper. Ta (tantalum) film is known as such a barrier film (see e.g., patent document 3).
FIGS. 18(a) to 18(e) are cross-sectional views showing one example of a process for forming a multilayer wiring structure using a Ta film as the barrier film.
Referring to FIG. 18(a), elements such as a transistor are formed on a substrate 200, which is a film formation subject. On the substrate 200, a first wire Cu film 251, a cap layer 252 formed to have a film thickness of about 10 to 30 nm, a first silicon dioxide film 253 functioning as an interlayer insulation film formed to have a film thickness of about 300 to 1000 nm, a tantalum nitride film 254 functioning as an etching stop film when a wire groove is etched and formed to a have a film thickness of about 30 to 200 nm, and a second silicon dioxide film 255 functioning as a second interlayer insulation film and formed to have a film thickness of about 300 to 1000 nm are sequentially superimposed.
Each of these films is formed through known methods. For example, the Cu film 251 is formed through electroplating etc., and the cap layer 252, first silicon dioxide film 253, and second silicon dioxide film 255 are formed through a CVD process.
A photoresist pattern is formed in these superimposed films through a normal exposure process and include a hole 256 and a wire groove 257 formed by anisotropic etching. A Ta film 258 serving as the barrier film is formed in the hole 256 and the wire groove 257 and on the second silicon dioxide film 255 through sputtering, as shown in FIG. 18(b).
Next, as shown in FIG. 18(c), a second Cu film 259 is formed on the entire surface of the Ta film 258 so as to fill the hole 256 and the wire groove 257. Thereafter, as shown in FIG. 18(d), the Cu film 259 formed on the Ta film 258 at a flat portion 551 of the second silicon dioxide film 255 is polished and removed through a chemical mechanical polishing (CMP) process. Then, as shown in FIG. 18(e), the Ta layer 58 exposed on the flat portion 551 is polished and removed through the CMP process. The Cu film 259 is thus filled only in the hole 256 and the wire groove 257.
The multilayer wiring structure is obtained by repeating the formation of copper wires and the formation of vias as described above.
However, if the Ta film 258 is used as the barrier film, the Ta film 258 remains on the second silicon dioxide film 255 when removing the Ta film 258 from the flat portion 551 (see FIG. 18(e)) and causes a characteristic defect of the semiconductor device.
[Patent Document 1] Japanese Laid-Open Patent Publication No. 2002-43315
[Patent Document 2] Japanese Laid-Open Patent Publication No. 2003-17496
[Patent Document 3] Japanese Laid-Open Patent Publication No. 2004-6856 (Claims etc.)